Silicon Almanac.All explainers
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The leading edge who is left

Only three left.

At 180 nm, 94 companies made chips. At 7 nm, three did. Each step down cost more, and fewer companies could make it pay.

Each step of the staircase is a process node, newer to the right. Each token is a company making chips at that node. Scroll to go on. Drag to turn.

94 → 3chipmakers, 180 nm to 7 nm
$542 Mto design one 5 nm chip, estimated
$29.8 bnTSMC's capital spending, 2024

Counts from CSET (2020), design cost from IBS as reported by Semiconductor Engineering (2018), capital spending from TSMC.

01 Company by company

Down the staircase.

Every node shrinks the transistor and adds cost. CSET's explanation: fixed costs rose faster than variable costs, raising the barrier to entry. At each step, some chipmakers stayed where they were. Many still make chips at those nodes; they stopped following.

180 nm
Chipmakers at this node94
Lithography suppliers4

CSET's Table 1, from SEMI's World Fab Forecast, May 2019. CSET's table counts three at 5 nm; its own text, from the same time, names only TSMC and Samsung in production there, with Intel still at 10 nm.

02 The year two stepped off

2018: two exits.

In August 2018, GlobalFoundries dropped its 7 nm programme, even with EUV scanners already installed in its New York fab. IEEE Spectrum wrote that this left "only three companies" on the top rungs: Intel, Samsung and TSMC.

A week later, UMC's co-president was asked whether UMC would move into 7 nm. His answer, to the Taipei Times: "No, we won't."

Both firms still make chips, at older nodes that most chips use. Leaving the leading edge is a business choice, not a failure.

03 Before a single wafer

The cost of a design.

Designing a chip at a new node means new rules, new tools, new verification and new masks. IBS estimated $51 million for a 28 nm design, $298 million at 7 nm and $542 million at 5 nm. In 2023 it put a large 2 nm chip at $725 million.

A leading-edge fab is harder still: IBS put a 3 nm fab for 40,000 wafers a month at $15 to $20 billion, plus $4 to $5 billion to develop the process.

IBS estimates as reported by Semiconductor Engineering (June 2018) and Tom's Hardware (August 2023). Estimates, from one firm, in two different years.

04 Arithmetic

How many chips pay for it?

Divide the design cost by what each chip earns after its own manufacturing cost. The answer is how many you must sell before the design has paid for itself.

$20
Chips to break even0
Tiles shown0

Design costs are the IBS estimates from the chapter before; the earnings per chip is yours to set. At $20 a chip, a 5 nm design needs about 27 million sales before it has paid for itself.

05 One year's bill

The price of staying.

Staying on the staircase is paid every year. In 2024 TSMC spent $6.4 billion on R&D and $29.8 billion on capital; for 2025 it planned $38 to $42 billion, about 70% for advanced processes. Intel spent $16.5 billion on R&D.

The tools are part of it. An EUV scanner costs around €170 million, and a High-NA one about €350 million, as reported from ASML's figures.

TSMC annual report and Q4 2024 earnings call; Intel 2024 results; scanner prices as reported by Tom's Hardware, citing Reuters and ASML (February 2024). The 2025 bar is drawn at the middle of the plan and is lighter because it is a plan.

06 A new entrant

Can anyone climb back?

Japan is trying. Rapidus, founded to make 2 nm chips, says it aims for full-scale production by 2027. It has raised 424.95 billion yen in equity, and Japan's industry ministry approved another 631.5 billion yen for its R&D in April 2026, as Reuters reported.

It is skipping the steps in between: from no leading-edge fab to 2 nm in one jump. Whether that works is the open question of this staircase.

Rapidus press releases, February and June 2026; Reuters via Investing.com, 11 April 2026. This page makes no call on the outcome.

07 Where to go next

The top of the staircase.

What those billions buy is in the other explainers.