Only three left
In SEMI's data of May 2019, as CSET counted it, 94 chipmakers were operating at 180 nm or smaller and 3 at 7 nm or smaller. This page follows that count node by node and sets the money beside it: what a design costs, and what one year of building costs.
The count, node by node.
For each node, CSET counted the chipmakers operating at that node or smaller in 2019, from SEMI's World Fab Forecast. Its reading: "Fixed costs increasing faster than variable costs has created higher barriers of entry, squeezing fab profits and shrinking the number of chipmakers operating fabs at the leading nodes."
At 5 nm the table counts 3. CSET's text of the same date says "there are only two chipmakers at the 5 nm node": TSMC and Samsung, with Intel at 10 nm and planning 7 and 5 nm. Move the slider.
2018: GlobalFoundries stops; UMC says no.
On 27 August 2018 GlobalFoundries said it was "putting its 7nm FinFET program on hold indefinitely" and moving its development to its 14 and 12 nm processes. It had installed at least one EUV machine at its Fab 8 in Malta, New York, IEEE Spectrum reported, and the move left "only three companies reaching for the highest rungs of the Moore's Law ladder: Intel, Samsung, and TSMC."
UMC had said in July 2017 that it would not allocate capital for process technologies below 14 nanometres, the Taipei Times recalled. A week after GlobalFoundries' release, asked whether UMC would redirect resources towards 7 nm, its co-president Chien Shan-chieh said, as the Taipei Times reported: "No, we won't."
Both still make chips. GlobalFoundries lists FinFET at 12 nm as its finest CMOS platform, made at its Malta fab. UMC says it began shipping 14 nm wafers in early 2017, and lists a 12 nm process under development with Intel Foundry. On the stand, the two step out of their row and stay at their node.
6 sites, one ground.
These are the operating fab sites in this record whose publishers name a process at 3 nm or smaller, or Intel 18A: Intel's Fab 52 in Chandler and D1X in Hillsboro, Samsung's V1 line in Hwaseong, and TSMC's Fab 18 in Tainan, Fab 20 in Hsinchu and Fab 22 in Kaohsiung. They are drawn from their mapped outlines on one ground at one scale, beside a football pitch.
The see-through blocks are phases OpenStreetMap tags as under construction: 2 at Fab 20 and 3 at Fab 22. Each label gives the footprint of the solid blocks alone. Samsung's fab in Taylor and Rapidus's IIM-1 are in this record as under construction, so they are not drawn.
The cost of a design.
IBS estimated the cost of designing a chip at $51.3 million at 28 nm, $297.8 million at 7 nm and $542.2 million at 5 nm, as Semiconductor Engineering reported in June 2018. In 2023 it put "a fairly large 2nm chip" at $725 million, as Tom's Hardware reported; Tom's Hardware notes that the figures assume a company that "has to develop everything from scratch".
In the same 2018 article, IBS's chief executive, Handel Jones, put a 3 nm fab for 40,000 wafers a month at $15 billion to $20 billion, and developing the process at $4 billion to $5 billion.
Each cube holds US$1 billion in US$100 notes: 10 million notes, a cube 2.24 m on a side. A design is a share of one cube; the fab is a pile, the top of its range drawn see-through.
How many chips pay for it?
Divide the design cost by what each chip earns after its own manufacturing cost. The answer is how many you must sell before the design has paid for itself. Pick a node and set the earnings.
The price of staying.
TSMC spent $29.8 billion on capital in 2024 and $40.9 billion in 2025. In July 2026 it raised its 2026 capital budget to $60 billion to $64 billion, about 70% to 80% of it for advanced process technologies. In January 2026 it said the capital needed to build capacity of 1,000 wafers a month at N2 is "substantially higher" than at N3.
Intel's gross capital expenditures were $17.7 billion in 2025. Samsung Electronics, across all its businesses, spent KRW 47.52 trillion on property, plant and equipment, about $33.4 billion at that year's average rate. Research and development comes on top, each in the unit its company states it in: in 2025 TSMC spent 6.5% of its revenue on it, Intel $13.8 billion and Samsung Electronics KRW 37.7 trillion.
A new entrant, dated.
Rapidus said in July 2025 that it had started prototyping 2 nm gate-all-around transistors at its IIM-1 fab in Chitose, Hokkaido, and that it "will begin mass-production in 2027". In June 2026 it gave its capital as 424.95 billion yen, and said it would keep raising capital and financing on the way to full-scale 2 nm manufacturing by 2027.
In April 2026 Japan's industry ministry approved another 631.5 billion yen for its research and development, Reuters reported. The stand draws Rapidus jumping from the ground to the glass tier; it has no earlier node on the stand.
The top of the stand.
The glass tier holds the three companies whose own statements of January 2026 say a 2 nm-class process of theirs is in high-volume or mass production: Intel (Intel 18A, which Intel calls "2-nanometer class"), Samsung (its first-generation 2 nm) and TSMC (N2). Each process name is the company's own.
Chipmakers on this record: GlobalFoundries, Intel, Rapidus, Samsung Electronics, SMIC, TSMC and UMC. Their fabs: the fab map.
- What a fab buyswhere a fab's money goes11
- What "2 nm" meanswhat a node's name measures07
- Wrapping the gatewhat a new node changes in the transistor06
- What a chip costshow many good chips one wafer gives10