The transistor goes 3D
Wrapping the gate.
A transistor is a switch. For fifty years it was a flat one. Then it stood up, and now it is turning into a stack of thin sheets with the gate wrapped all the way round.
This page shows why each step was forced, not chosen, and where it goes next.
01 The planar transistor
A gate that opens a road.
Electrons wait in the source and want to reach the drain. Between them lies a strip of silicon that does not conduct, the channel. A voltage on the gate, sitting on top behind a thin insulator, pulls a thin conducting layer into existence just under the surface. Switch it off and the road disappears.
02 Why flat stopped working
Shrink it, and off is not off.
The gate controls the silicon from above only. With a long gate that is enough. As the gate shrinks, source and drain crowd each other, and current starts to sneak underneath, through silicon the gate cannot reach. The switch leaks even when it is off, and a billion leaking switches is a hot, wasteful chip.
The leakage curve is illustrative: it grows roughly exponentially as the gate shortens, which is the shape that matters, not the numbers.
03 FinFET
Stand the channel up.
If the gate cannot reach deep enough, make the channel thin enough that it does not have to. A FinFET turns the channel into a tall, thin fin and drapes the gate over it, controlling it from three sides. Intel announced the first production FinFET, its 22 nm "tri-gate", in 2011. Every leading chip for the next decade used fins.
Both are shown switched off.
04 Nanosheets
Wrap it on all four sides.
Fins could only get so thin and so tall. The next step lays the channel flat again, as thin sheets stacked on top of each other, and fills the gaps with gate. Now the gate surrounds every sheet completely. And unlike a fin, a sheet's width is a design choice: wider for more current, narrower for less power.
Samsung introduced gate-all-around at 3 nm in 2022. TSMC's N2, its first nanosheet process, entered volume production in the fourth quarter of 2025, claiming 10 to 15% more speed or 25 to 30% less power than N3E. Intel calls its version RibbonFET, in 18A. The ratio shown is geometry of this drawing.
05 Backside power
Feed it from below.
Above the transistors sits a dense stack of wiring. Until now, power and signals shared it, and the fat power lines ate space the signals needed. Backside power delivery flips the wafer, thins it away, and runs the power network underneath the transistors. The top is left for signals.
Intel ships backside power as PowerVia in 18A. TSMC's version, Super Power Rail, comes with A16, planned for volume production in the second half of 2026.
06 What comes next
Stack the transistors themselves.
Logic is built from pairs: an n-type and a p-type transistor working together. Today they sit side by side. The research roadmap from imec runs nanosheet, then forksheet, then CFET, where the two are stacked on top of each other.
Footprints are illustrative. imec positions CFET for nodes beyond 1 nm-class, with 2D materials as a later step.
07 Where to go next
Every step, forced.
Each architecture change bought one more generation of control over a switch a few dozen atoms long. Each also needed new etch, new deposition, and a sharper print from the scanner.
- Sculpting in atoms: how sheets and gaps are etched and filled
- Writing with light: printing the pattern in the first place
- Chips on chips: stacking the finished dies
Every figure comes from a publisher named below. Devices are drawn schematically, not to scale.