Wrapping the gate

A gate that opens a road.

Electrons wait in the source and want to reach the drain. Between them lies silicon that does not conduct, the channel. A voltage on the gate, sitting on top behind a thin insulator, pulls a conducting film of electrons into being just under the surface; Chenming Hu's textbook puts it at 1 to 2 nm thin. Switch the gate off and the road disappears.

The insulator is thinner still: Intel's gate oxide at its 65 nm node was 1.2 nm, which Intel says is equal to 5 atomic layers. And a chip holds billions of these switches: IBM says its 2 nm test chip of 2021 fits up to 50 billion transistors on a chip the size of a fingernail.

Shrink it, and off is not off.

The gate controls the silicon from the top only. As it shrinks, source and drain crowd each other, and the drain pulls electrons across along paths below the surface, where, in Hu's words, the gate is far away and its control is weak. The switch leaks even when it is off.

Hu calls it drain-induced barrier lowering. Rapidus writes that in a planar transistor the current when off rises rapidly once gates approach about 20 nm.

Stand the channel up.

If the gate cannot reach deep enough, make the channel thin enough that it does not have to. A FinFET stands the channel up as a thin fin and drapes the gate over it, so the gate holds it from three sides: top, left and right, in Intel's words. Hu's rule of thumb: leakage is well suppressed if the fin is no thicker than the gate is long.

Hu, Jeff Bokor and Tsu-Jae King Liu's team at UC Berkeley named the FinFET in 1999. Intel announced its 22 nm tri-gate, a FinFET, in May 2011. The fins drawn here are Intel's at 14 nm: 8 nm wide, 42 nm tall, 42 nm apart. 8 nm is about 15 of silicon's cubic unit cells.

Wrap all four sides.

imec writes that each generation of fins got taller, thinner and closer, which cut their drive strength. Nanosheets lay the channel flat again, stacked, with the gate in every gap.

A sheet's width is a design choice: IBM made nanosheets 15 to 70 nm wide, with a gate 12 nm long that IBM calls just two dozen atoms long. Our arithmetic: 12 nm ÷ 0.5431 nm is 22 of silicon's unit cells.

Feed it from below.

Above the transistors sits a dense stack of wiring: Intel wrote in 2023 that its Intel 4 process has 18 metal layers. Until now, power and signals shared it. Intel writes that the power wires can take up to 20% of the front side, and imec that power interconnects take at least 20 percent of the routing. Backside power delivery flips the wafer, thins it and runs the power network underneath the transistors, through nano-scale vias. The top is left for signals.

Stack the transistors themselves.

Logic is built from pairs: an n-type and a p-type transistor working together. Today they sit side by side. imec's roadmap runs from nanosheet to forksheet, with a dielectric wall between the two, and then to CFET, where the two are stacked on top of each other.

One side, three, then all four.

Each architecture gave the gate more of the channel: the top of a flat one, three sides of a fin, all four of a sheet; imec foresees stacked pairs from its A7 node. Intel wrote in 2012 that more than 4,000 gates of its 22 nm transistors would fit across a human hair. Each also needed new steps: in imec's description the sheets start as stacked silicon and silicon-germanium, and the silicon-germanium is removed later.

Chipmakers on this record: Intel, Rapidus, Samsung Foundry and TSMC; research: imec. SEMI's figure for installed capacity at 2 nm and below is on its figure page, and the fabs are on the fab map.

• Sculpting in atomshow sheets and gaps are etched and filled05
• What “2 nm” meansnode names against real sizes07
• Writing with lightprinting the pattern in the first place03