The leading edge naming

What "2 nm" means.

Nothing on a "2 nm" chip is 2 nanometres. The name is a label for a generation, like a model year, and has not measured anything on the chip since the 1990s.

The scene is a patch of transistors at the pitches reported for TSMC N2, drawn to scale: amber gates, copper metal lines above. The red bar is how long 2 nm would be, drawn ten times too big so you can see it.

1997when node names stopped matching gate length, per Intel

~48 nmgate pitch on "2 nm" and "3 nm" nodes

0.543 nmspacing of silicon's crystal lattice

Intel press release, July 2021; pitches from the sources in chapter 02; lattice constant from NIST.

01 Down to the atoms

How long is 2 nm?

Zoom from a patch of gates down to the silicon itself. Two nanometres spans fewer than four spacings of silicon's crystal lattice. No transistor feature in production is that small.

Zoom160 nm

2 nm is3.7 lattice spacings

View widthapproximate, on a wide screen

Lattice constant 0.5431 nm (NIST CODATA 2018); atomic radius 111 pm (Wikipedia). The gate length range is from an IRDS More Moore workshop deck (November 2023). As Paolo Gargini, IRDS chair, told IEEE Spectrum: the node number "had nothing to do with any dimension that you can find on the die."

02 What to measure instead

Two pitches tell the truth.

Engineers compare nodes by two spacings: the contacted gate pitch, from one transistor gate to the next, and the minimum metal pitch, between the finest wires. Pick a node; the patch is redrawn to scale.

Gate pitch0

Metal pitch0

Source-

Bars behindgate pitch, then metal pitch

Foundries rarely publish pitches; most figures are from teardowns, conference papers or Wikipedia's compiled tables, and each is labelled. TSMC N5 is the measured value from Angstronomics (a WikiChip pre-silicon estimate was 48 / 30). From N7 to N2, gate pitch shrank from 57 nm to 48 nm. The name shrank from 7 to 2.

03 2021

A node renamed overnight.

In July 2021 Intel renamed its nodes. "10nm Enhanced SuperFin" became Intel 7; what had been Intel 7nm became Intel 4. Nothing on the chips changed. Intel's reason: "the various naming and numbering schemes used across the industry no longer refer to any specific measurement."

Side by side, Intel 7 and TSMC N7 are close cousins: 60 against 57 nm gate pitch, both 40 nm metal pitch. By pitch, Intel's old name had undersold its node against TSMC's.

Intel fact sheet and press release, 26 July 2021. Intel 7 pitches from Wikipedia; TSMC N7 from WikiChip.

04 A better number

Count the transistors.

Transistors per square millimetre is closer to what a node buys. Each amber cube is a million transistors on one square millimetre.

Transistors per mm²0

Source-

Densities depend on which cell library is counted; these are the densest logic cells. Wikipedia lists N5 lower, at 138.2 million. For newer nodes TSMC publishes only ratios: N3 "up to 1.6X logic density" over N5, and N2 ">1.15x chip density" over N3. IEEE Spectrum has proposed a three-number metric, LMC: logic, memory and connection density.

05 After the pitch stops

The future is up.

The industry roadmap, IRDS, now labels nodes by what they are. "G45M20" means a 45 nm gate pitch and a 20 nm metal pitch. From 2031 a "T" appears: tiers of transistors stacked on top of each other. The pitches almost stop shrinking; the chip grows upward.

IRDS label-

Marketing name-

Tiers1

Statusa roadmap, not a promise

IRDS 2022, Lithography chapter, table LITH-2. By 2037 the roadmap's "0.5 nm" node still has a 38 nm gate pitch.

06 Where to go next

Read the pitch, not the name.

The name tells you the generation. The pitches and the density tell you what you get.

Wrapping the gate: the transistor inside the pitch
Only three left: who can still make these nodes
Writing with light: how a 20 nm pitch is printed at all