What “2 nm” means
A node’s name stopped measuring the chip long ago: Intel said in 2021 that node names stopped matching the gate length in 1997. The patch drawn here is the industry roadmap’s own “2 nm”: its gates stand 48 nm apart, 24 times the name.
How long is 2 nm?
Slide from a virus down to silicon’s crystal, every object at its true size. The 2 nm bar spans 3.7 of silicon’s unit cells. Some layers are thinner than the name: Intel’s 65 nm transistors had a gate oxide 1.2 nm thick, which Intel put at 5 atomic layers.
Paolo Gargini, then chairman of IRDS, told IEEE Spectrum in 2020 that the node number had “nothing to do with any dimension that you can find on the die”.
SARS-CoV-2, 89.8 nm across on average. To its right, a gate pitch and a metal pitch at the same scale.
Two gates 48 nm apart, centre to centre: the gate pitch IRDS gives its “2 nm” node.
The finest metal lines, 22 nm apart: IRDS’s tightest metal pitch for “2 nm”.
One gate 12 nm long: IBM’s 2 nm test chip of 2021, “just two dozen atoms long” in IBM’s words.
A strand of DNA is 2.5 nm wide, a little wider than the name.
The red bar is 2 nm, laid on silicon’s crystal: each tick marks one unit cell, 0.543 nm.
Two pitches.
Intel’s Mark Bohr wrote in 2017 that one simple metric is gate pitch times minimum metal pitch, each a width plus the space beside it. Pick a node: the patch is redrawn at both, its name beside them.
Not drawn: TSMC N2, its IEDM 2024 paper has “no pitches” (SemiWiki); TSMC N3, its 2022 papers gave N3’s gate pitch (45 nm) and N3E’s metal pitch (23 nm); Samsung, area ratios only.
A node renamed.
In July 2021 Intel renamed its nodes: “10nm Enhanced SuperFin” became Intel 7, and “Intel 7nm” became Intel 4. Intel’s sentence on naming: “the various naming and numbering schemes used across the industry no longer refer to any specific measurement”. Its next names end in A, and Intel said 20A “ushers in the angstrom era”.
Intel’s slide of 2023 gives Intel 7 a gate pitch of 54 or 60 nm and a metal pitch of 40 nm. Angstronomics gives TSMC’s N7 57 and 40 nm.
Count the transistors.
Bohr also proposed that chipmakers state logic transistor density in millions per square millimetre, by a formula that weights a small cell 0.6 and a large one 0.4. A million per mm² is one per µm²: the square, a micrometre a side, holds that many, rounded. Behind it, an E. coli bacterium, about 1 by 2 µm.
TSMC states ratios: N3 “up to 1.6X logic density gain” over N5, N2 “>1.15x chip density increase” over its 3 nm. Philip Wong and others proposed in 2020 to count logic, memory and packaging/integration together.
The roadmap stacks up.
IRDS, the IEEE’s roadmap, labels a node by lengths: “G48M22” is a 48 nm gate pitch and a 22 nm tightest metal pitch, “/T2” two tiers. Its 2024 edition takes the gate pitch from 48 nm (2024) to 42 nm (2039), with a CFET, n-type over p-type, from 2031 and tiers from 2035.
Two pitches, from above.
From above, the gate lines run one way and the metal lines the other: the roadmap’s “2 nm” at 48 and 22 nm, the name a red sliver among them.
Chipmakers on this record: Intel, Rapidus, Samsung Foundry and TSMC; research: imec. Which fabs run which named node, in SEMI’s bands, is on the nodes page; SEMI’s capacity at 2 nm and below is on its figure page.
- Wrapping the gatethe transistor inside the pitch06
- Only three leftwho makes these nodes13
- Writing with lighthow a pitch is printed03