What a chip costs
A chip's price starts with three numbers: how many fit on a wafer, how many of those work, and what the wafer cost. This page counts the first two live and lets you set the third.
Squares on a circle.
Chips are rectangles; wafers are round. Every die has to fit whole inside the usable area, so the edge of the wafer is always lost, and the squares it cuts through, hatched here, are thrown away. The bigger the die, the more of the edge it cannot use.
The coin is a €2 coin, 25.75 mm across. The largest die one exposure can print is 26 × 33 mm, 858 mm²; NVIDIA's H100 die fills 95% of it.
Where a speck lands, a chip dies.
A killer defect is any physical flaw that makes a circuit fail. A fab counts them as defect density, D0, killer defects per square centimetre. In the simplest picture they land at random, so a small die usually slips between them and a big die is a big target.
The simplest model, named after Poisson, says the share of dies with no killer defect is e−A·D₀ for a die of area A. Scatter a wafer and set it beside the model.
Clumps kill fewer chips.
Real defects tend to cluster. Several defects in one die kill it only once, so a wafer whose defects clump keeps more good dies than one with the same number spread out. That is why the Poisson model tends to underestimate the yield of large dies.
Both wafers carry the same number of killer defects. Murphy's model, from Bell Labs in 1964, lets the density vary across the wafer: set a large die and a high D₀, and watch the two models part. The clustered wafer is our own picture of clumping, not what Murphy's model predicts, so its count and Murphy's yield need not agree.
Big dies pay twice.
Divide the wafer price by the good dies on it. A die eight times bigger costs more than eight times as much: fewer fit, and more of them are hit. The white plates show where each column would stop if cost grew with area alone.
No foundry we read publishes a price per wafer, so set your own. It starts at $20,000, the price of a 3 nm wafer in TrendForce's summary of an EE Times report (October 2025).
TSMC's revenue per wafer is its revenue over the wafers it shipped, our arithmetic: US$6,983 in 2024 and US$8,161 in 2025. GlobalFoundries: US$3,178 in 2024. Not a price TSMC states: it blends every node, and TSMC's revenue holds more than wafers.
A big die can be cut into pieces.
Split a big design into chiplets joined in the package, and a defect scraps a quarter of the silicon. The price is extra silicon for the links between them and a package that joins them, the subject of Chips on chips.
AMD made this case for its EPYC server processor at Hot Chips in 2017: four dies of 213 mm², 852 mm² in all, against one hypothetical die of about 777 mm², at 0.59 times the cost by AMD's own yield model. Here is that example at your settings.
Geometry, luck and a price tag.
Everything a fab does to lower defect density, and everything a designer does to shrink a die, shows up in the cost of one good chip. This is your wafer from chapter 02.
Named on this page, and on this record: AMD, GlobalFoundries, Intel, NVIDIA and TSMC; Canon and Nikon, which make lithography scanners; and DISCO, which makes dicing saws. Where the wafers are made: the fab map.
- Chips on chipspackaging the chiplets back together09
- Anatomy of a fabwhere defects come from, and how the building fights them02
- Writing with lightwhy one exposure field caps the die size03
- What a fab buyswhere the money for the wafers goes11