Chip economics from the wafer up
What a chip costs.
A chip's price starts with three numbers: how many fit on a wafer, how many of those work, and what the wafer cost.
Every yellow speck on this wafer is a killer defect. Every die it lands on is scrap. Change the numbers in the chapters below and watch what happens to the cost of one good chip.
Wafer prices are not published by any foundry. The figures here are press reports, labelled as such, and every price on this page is one you can change.
01 Dies per wafer
Squares on a circle.
Chips are rectangles; wafers are round. Every die has to fit whole inside the usable area, so the edge of the wafer is always wasted. The bigger the die, the more of the edge it cannot use.
The count is geometry, done live: square dies laid on a grid, the best of four grid positions kept. H100 die size from NVIDIA's Hopper whitepaper; the 858 mm² limit is one scanner field.
02 Yield
Where a speck lands, a chip dies.
Killer defects land at random. A fab measures them as defect density, D0, in defects per square centimetre. A small die usually slips between them. A big die is a big target.
The model is the simplest one, Y = e−A·D₀. Real defects cluster, so real yields for big dies are usually better than it says. For scale: TSMC reported about 0.09 defects per cm² for N7 and 0.10 to 0.11 for N5 during their 2020 ramps.
03 Cost per good die
Big dies pay twice.
Divide the wafer price by the good dies on it. A die eight times bigger costs far more than eight times as much, because fewer fit and a larger share of them are hit.
Silicon only. Masks, design, testing, packaging and memory all come on top, and for an AI accelerator the package and its HBM can cost more than the die. Reported prices from TrendForce, citing supply-chain sources; foundries do not publish them.
04 The way out
Cut the big die into pieces.
If big dies are expensive because one defect scraps the whole thing, split the design into smaller chiplets and join them in the package. A defect now scraps a quarter of the silicon, not all of it.
The price is extra area for the connections between chiplets, and a harder, costlier package. That is the trade the "Chips on chips" explainer is about.
Illustrative: the overhead is your assumption, packaging cost is left out, and chiplets are tested before assembly so only good ones are used.
05 Where to go next
Geometry, luck and a price tag.
Everything a fab does to lower defect density, and everything a designer does to shrink a die, shows up in the one number at the bottom of this page.
- Chips on chips: packaging the chiplets back together
- Anatomy of a fab: where defects come from, and how the building fights them
- Writing with light: why one scanner field caps the die size
Every figure comes from a publisher named below. Counts and yields on this page are calculated live from your settings.