Starting the clock
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The chip at work · Explainer 18

A billion ticks a second

A chip's circuits work to a beat, its clock. A 4 GHz clock ticks four billion times a second, and Qualcomm gives its Snapdragon 8 Elite Gen 5 phone chip a clock of up to 4.74 GHz.

0.25 nsone tick at 4 GHz, our arithmetic
3.8 GHzthe last Pentium 4 clock The Register reports, 2004
9.19 billionthe SI's second: 9,192,631,770 ticks of a caesium atom
Scene: a chip package on a board, its memory beside the die, and its clock drawn as a square wave that a bead of light follows, one period a tick; generic and drawn. 4.74 GHz: Qualcomm. 3.8 GHz: The Register (press, November 2004). The second: the BIPM's SI Brochure. Sources are listed at the end.
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01 · The clock

How long is a tick?

The clock is a signal that flips between 0 and 1 at a steady rate, and the circuits move in step with it. At 1 GHz a tick lasts one nanosecond, and light covers about 30 cm in it; at 3.50 GHz, one bank card's width.

A signal in a wire meets RC delay, from the wire's resistance and capacitance: Intel wrote in 2005 that RC delays were growing as features shrink.

One tick
0.25 ns
Light, per tick
7.5 cm
Memory read, ticks
320
Light per tick: our arithmetic from the speed of light, which the BIPM fixes at 299,792,458 m/s. Card: 85.60 × 53.98 mm, ISO/IEC 7810 as ICAO restates it; €2 coin: 25.75 mm, European Central Bank; both at true size, the chip drawn. Wires: Intel (2005). Memory: about 80 ns for an idle random read from DRAM, on the system Intel's optimization manual (2023) measured; the ticks are ours. 5.7 GHz: the boost clock Intel gives for its Core Ultra 9 285K and AMD for its Ryzen 9 9950X, both of 2024.
02 · 2005

Clocks levelled off after 2005.

Intel's Pentium 4 reached 3.06 GHz in November 2002 and 3.8 GHz in 2004. In October 2004 Intel dropped a planned 4 GHz part; its first dual-core PCs went on sale in April 2005, at 3.2 GHz. The CPU DB authors wrote in 2012 that processor frequency had largely levelled off since 2005.

Dennard's team at IBM showed in 1974 that shrinking a transistor and its voltage together keeps power per area constant; in 2007 Intel's Mark Bohr wrote that leakage made voltage hard to scale. Pick Voltage in the switch.

1995, middle of 391995, middle of 351995, middle of 151995, middle of 321995, middle of 39
200 MHz3.3 V16 W5.2 million1
2004, middle of 172004, middle of 172004, middle of 172004, middle of 172004, middle of 17
2.6 GHz1.40 V84 W125 million1
2009, middle of 942009, middle of 792009, middle of 942009, middle of 802009, middle of 94
2.6 GHz1.36 V80 W731 million4
Dots: Stanford's CPU DB (Danowitz, Kelley, Mao, Stevenson, Horowitz), used as published for download, with no licence stated; it ends in 2014, clocks are nominal, and each dot sits at its year at a random place, as 648 of the 649 rows from 2011 to 2014 read January. Left out: two Atoms at 21,300 MHz, a Xeon at 13,625 V, six rows at 0 V. Amber, not CPU DB: The Register (press, 2004: the Pentium 4, the dropped 4 GHz part); Intel (2005); Intel and AMD (2024), boost 5.7 GHz and, smaller, base 3.7 and 4.3 GHz; Apple (2025). Readouts: each year's middle processor, ours. Intel (2002); Dennard et al. (IEEE, 1974); Bohr, Intel (2007).
03 · Doing more per tick

Several instructions a tick.

Intel wrote in 2006 that performance is frequency times instructions per clock cycle. A core fetches several instructions at once and runs them side by side.

Intel's cores of 2006 handled up to four at a time, three before; its 12th-generation Core chips decode up to six a cycle, and AMD's 2024 core dispatches eight operations a cycle. Apple says only that M4's performance cores decode wider.

At most, per second, one core
32.0 billion
Intel: its Core microarchitecture white paper (2006) and optimization manual (2023). AMD: Zen 5 at Hot Chips (August 2024). Apple: M4 (May 2024). Each counts a different stage, decode or dispatch. The ceiling is our arithmetic, instructions times ticks. The core's floor plan is drawn, not any company's.
04 · Doing more at once

More cores, side by side.

The second answer: several cores on one chip, each with its own stream of instructions. Intel's first dual-core PCs went on sale in April 2005. AMD's EPYC 9965 of 2024 has 192 cores; Intel's Xeon 6990E+ of 2026 has 288 cores of the kind Intel calls efficient. Apple's M4 has up to four performance and six efficiency cores.

A third answer is a block for one kind of maths: Apple gives M4's Neural Engine up to 38 trillion operations a second.

Peak, billion a second
128
Neural Engine ops against it, not like for like
297×
Intel (April 2005). AMD: its EPYC 9965 page. Intel: its Xeon 6+ page, launch Q2 2026. Apple: M4 (May 2024), "up to" as Apple writes it. The peak, in instructions, and the ratio are our arithmetic on your settings; an operation is not an instruction. The die is drawn.
05 · System on a chip

One package, many blocks.

Apple calls M4 a system on a chip: CPU cores, graphics, the Neural Engine, caches and links to memory in one chip, beside one pool of memory. Joining dies in one package is the subject of Chips on chips.

M3 Ultra and M5 Ultra do both: M3 Ultra links two M3 Max dies over 10,000 high-speed connections, and M5 Ultra, of August 2026, joins four dies.

Build
one chiptwo diesfour dies
Transistors
28 billion184 billionnot stated
CPU cores
4 + 624 + 812 + 24
Memory bandwidth
120 GB/sover 800 GB/s1.2 TB/s

CPU cores as Apple counts them, at most: performance and efficiency; for M5 Ultra, super and performance.

Apple Newsroom: M4 (May and October 2024), M3 Ultra (March 2025), M6 and M5 Ultra (August 2026). Apple states no transistor count for M5 Ultra and no die count for M4. The floor plans are drawn: Apple publishes no block areas.
06 · Where to go next

More per tick, more cores.

Intel wrote in 2005 that clock frequency had brought roughly 80 percent of performance gains until then; the CPU DB authors wrote in 2012 that at the power wall the industry turned to chips with many simple processors. From 2004 to 2024 the clock went from 3.8 GHz rated to a 5.7 GHz boost, 1.5 times; against base clocks of 3.7 and 4.3 GHz, 0.97 and 1.13 times, our arithmetic.

Named on this page, and on this record: AMD, Apple, Intel and Qualcomm.

80 percent: Intel, Platform 2015 (2005). Power wall: the CPU DB authors (2012). 3.8 GHz: The Register (press, 2004); 5.7, 3.7 and 4.3 GHz: Intel and AMD (2024); the ratios are ours. The package is the one from the start.