Where a chip gets made
In SIA and BCG's account, the typical journey of a chip involves most if not all of six regions: the US, South Korea, Japan, mainland China, Taiwan and Europe. This page splits the work into eight kinds, shows where the firms that do each have their headquarters, and follows one chip around the world.
Eight kinds of work.
Georgetown's CSET split the industry's value added into eight segments, by its own estimate from 2019 revenues. Making chips in fabs and designing them are the two largest, 38.4% and 29.8%: together 68.2% of the whole, by our arithmetic. The two smallest are design software, 1.5%, and licensed cores, 0.9%.
The tray is the whole industry. Each block's top is its share, all at one scale, and on each block stands the kind of work as a thing. Pick a segment.
Wafer fabrication turns designs into chips (CSET). CSET counts the fab's materials other than wafers, such as electronic gases, wet chemicals and the materials for deposition and polishing, inside this slice.
Chip design, in CSET's list: specification, logic design, physical design, and validation and verification. Designers work in design software and license building blocks, the two smallest slices.
Fab tools: the machines for lithography, deposition, etch, ion implantation, cleaning, polishing and process control, among others (CSET).
Assembly, test and packaging: the finished wafer is cut into chips, and each is mounted, wired to the outside, enclosed and tested (CSET). CSET counts packaging materials in this slice.
Wafers: the thin silicon discs chips are made on, and only those. CSET counts the fab's other materials inside wafer fabrication.
Packaging and test tools: the machines that dice wafers, bond and package chips, and test them (CSET).
Design software, known as EDA. In CSET's words, US firms are “the exclusive providers” of EDA software with the full set of capabilities needed to design leading-edge chips.
Core IP: reusable parts of chip designs that design firms license and build into their own (CSET).
Who does what.
Pick a segment and the map shows where the firms that do it have their headquarters, in CSET's count. By that count, US firms hold 39% of the whole industry, 47% of chip design and 96% of design software. Japanese firms hold 56% of wafers and 44% of packaging and test tools. In wafer fabrication, US firms hold 33%, South Korean firms 22% and Taiwanese firms 19%. In assembly, test and packaging, Taiwanese and US firms hold 29% and 28%.
Around the world in six stops.
Follow one phone processor along the route SIA and BCG drew as an illustration in 2021, not any company's chain. Drawn here, it crosses 11 borders. GSA and Accenture estimated that a chip could cross approximately 70 or more, and gave no method for the count.
Designed in the United States: a US firm designs the chip in US design software, on a processor architecture licensed from a European firm.
Wafers: silicon refined in the United States is grown into a crystal in Japan, then sliced and polished into wafers in South Korea.
Tools: firms in the United States, Japan and Europe develop the fab's machines.
Made in a Taiwanese foundry. In SIA and BCG's figures a fab takes about 12 weeks to make finished wafers, and for advanced processes it “can take up to 14-20 weeks”.
Cut apart and packaged in Malaysia. In 2022 Southeast Asia held about 20% of the world's assembly, test and packaging capacity, and Malaysia the largest share of it.
Built into a phone in China, and sold in the United States.
More than 50 chokepoints.
SIA and BCG counted more than 50 points in the chain where one region holds over 65% of the world market. Five of them:
Design software: US firms held 96% of it by headquarters in 2019 (CSET). By TrendForce's estimate, three firms held 75% of the market in 2021: Synopsys 32%, Cadence 30% and Siemens EDA 13%.
EUV scanners, the most advanced lithography tools. In CSET's words, “One Dutch firm, ASML, exclusively produces EUV scanners”, in its 2019 data.
Photoresist: Japan's share of the world market is put at 50% to 90%, depending on the estimate. The US International Trade Administration gives both on one page: 50%, citing Brookings, and about 90% for Japanese firms such as JSR and Tokyo Ohka Kogyo, naming no source. CSET's 90% cites a Reuters item of 2 July 2019.
Leading-edge fabs: in 2019, 92% of the world's capacity below 10 nm stood in Taiwan and 8% in South Korea (SIA and BCG), counted by where the fabs are.
Phone processor designs: SIA and BCG list Arm's architecture among their points. Arm says more than 99% of smartphones are built on Arm, a claim about phones, not a region's share. Arm has its headquarters in the UK, which CSET counts in Europe.
Redrawing the map.
In May 2024 SIA and BCG projected that the US share of the world's capacity for advanced logic, below 10 nm, would rise from 0% in 2022 to 28% by 2032. In their chart Taiwan and South Korea held 69% and 31% of it in 2022; for 2032 they forecast 44% elsewhere, by our arithmetic. BCG also expects packaging and test to spread from mainland China and Taiwan to Southeast Asia, Latin America and Eastern Europe, while the report says those two will keep the largest share.
Every stop has a story.
The other explainers go inside the stops on this route.
Firms this page names, on this record: Arm, ASML, Cadence, JSR, Siemens EDA, Synopsys and Tokyo Ohka Kogyo; and the Semiconductor Industry Association.
- From sand to waferhow a wafer is grown, sliced and polished01
- Anatomy of a fabthe building a wafer goes into02
- Chips on chipshow AI chips are packaged09
- Only three leftthe chipmakers at each node, as CSET counted them13