Precision times speed
The impossible machine.
Plenty of machines are precise. Plenty are fast. A lithography scanner is both at once, and the combination is what no other machine on earth attempts.
Its reticle stage accelerates harder than a fighter pilot can stay conscious. Then it stops, and every layer it prints lands on the one below to within a few silicon atoms.
All figures on this page are ASML's own published numbers for its High-NA EUV system, unless a line says otherwise.
01 The trade-off
Fast or precise: pick one.
Anything heavy that moves fast overshoots and rings when it stops. You can go slowly and land exactly, or go fast and wait for the wobble to die. Watch the amber trace.
A scanner refuses the trade. It has to arrive fast and be still on arrival, because it prints while it moves.
An illustration of a damped moving mass, not a model of a real stage. In a scanner the ringing is removed by stiff structure, counter-masses and control, which this page does not go into.
02 Two stages, one image
Racing in opposite directions.
The lens shrinks the reticle's image, so the reticle must sweep a longer distance than the wafer in the same moment, in the opposite direction. On a standard EUV scanner the image shrinks 4×. High-NA optics shrink it 8× in the scan direction, so the reticle travels eight times as far as the wafer, in the same time.
ASML: the EXE reticle stage accelerates at 32 g, four times the NXE, and the wafer stage at 8 g, twice the NXE. The NXE figures shown are derived from those two sentences. ASML's own comparison: 32 g is a race car going from 0 to 100 km/h in 0.09 seconds.
03 The hidden cost of High-NA
Half the field, twice the stops.
The price of 8× shrink in one direction: each exposure covers half the area. A wafer needs twice as many fields, so twice as many accelerations, sweeps and stops. To keep up, the stages had to get much faster. That is the real reason for 32 g.
Throughput: over 185 wafers an hour for EXE:5000 per ASML, and 160 at a 30 mJ/cm² dose for NXE:3600D per ASML's 2022 EUVL presentation. The average per field includes every wafer swap, alignment and measurement, so the actual exposure sweep is shorter still.
04 Freeze the frame
Landing on the layer below.
Every layer has to sit on the one printed before it, often on a different scanner, days earlier. The error between them is called overlay. ASML specifies under 0.8 nm for EXE:5000 on matched machines. That is about three silicon atoms.
The wireframe shows where the upper layer should sit; the violet column is where it lands. The line below is 8 nm wide, the smallest feature ASML quotes for High-NA.
05 Make it human-sized
A country-sized wafer.
Blow everything up by 1.25 million, until 0.8 nm becomes 1 mm. The wafer is now 375 km across. Each field is a rectangle of 32 × 21 km.
At that scale the machine jumps to a new 32 km field roughly nine times a second, sweeps it, and puts every line within a millimetre of where the layer below expects it. Without stopping for the rest of the day.
Derived: time per field is the published throughput divided by the fields on this wafer, including all overheads. The scaled distances are arithmetic, not measurements.
06 The paradox
A sprinter in a slow factory.
A leading-edge wafer spends 80 to 100 days in the fab. Semiconductor Engineering puts its time under the scanner at about a minute per layer. Across 80 layers that is little more than an hour: about 0.06% of its life.
The rest is waiting, moving, etching, filling and measuring. One High-NA scanner can serve a vast number of wafers precisely because it spends so little time with each, which is also why a fab can afford a machine this expensive at all.
Days and minutes from Semiconductor Engineering, "Battling fab cycle times". The 0.06% is arithmetic on those figures.
07 Where to go next
Fast, still, and exact.
Either half would be an achievement. The product of the two is why a scanner is the single most complex machine in the fab.
- Writing with light: what the scanner is printing
- Anatomy of a fab: the slow factory around it
- Sculpting in atoms: what happens to each print next
- Chips on chips: HBM and advanced packaging
- Wrapping the gate: how the transistor went 3D
Every figure comes from a publisher named below. Stage behaviour is illustrated, not modelled.